Illustrated in FIG. 1 is a conventional packaged integrated circuit (IC) device 100. The IC device 100 includes a die 110 that is disposed on a substrate 120, this substrate often referred to as the “package substrate.” The die 110 may comprise a microprocessor, a network processor, or other processing device. Die 110 may be coupled with the substrate using, for example, a Controlled Collapse Chip Connection (or “C4”) assembly technique, wherein a plurality of leads, or bond pads, on the die 110 are electrically connected to a corresponding plurality of leads, or lands, on the substrate 120 by an array of connection elements 130 (e.g., solder bumps, columns, etc.). Circuitry on the package substrate 120, in turn, routes the die leads to locations on the substrate 120 where electrical connections can be established with a next-level component (e.g., a motherboard, a computer system, a circuit board, another IC device, etc.). For example, the substrate circuitry may route all signal lines to a pin-grid array 125—or, alternatively, a ball-grid array—formed on a lower surface of the package substrate 120. The pin-grid (or ball-grid) array then electrically couples the die to the next-level component, which includes a mating array of terminals (e.g., pin sockets, bond pads, etc.).
During operation of the IC device 100, heat generated by the die 110 can damage the die if this heat is not transferred away from the die or otherwise dissipated. To remove heat from the die 110, the die 110 may ultimately be coupled with a heat sink 170 via a number of thermally conductive components, including a first thermal interface 140, a heat spreader 150, and a second thermal interface 160. Generally, a thermal interface is a component that fills in small pits and other surface irregularities on two mating solid surfaces and, further, that provides a thermally conductive path between these mating surfaces, such that the two solid surfaces are thermally linked. A typical thermal interface comprises a layer of a conductive material, such as a solder or a thermal grease.
The first thermal interface 140 is coupled with an upper surface of the die 110, and this thermal interface conducts heat from the die and to the heat spreader 150. Heat spreader 150 conducts heat laterally within itself to “spread” the heat laterally outwards from the die 110, and the heat spreader 150 also conducts the heat to the second thermal interface 160. The second thermal interface 160 conducts the heat to heat sink 170, which transfers the heat to the ambient environment. Heat sink 170 may include a plurality of fins 172, or other similar features providing increased surface area, to facilitate convection of heat to the surrounding air. The IC device 100 may also include a seal element 180 to seal the die 110 from the operating environment, wherein the seal element 180 and heat spreader 150 may comprise an integrated cap or housing for the die 110.
The heat sink 170, heat spreader 150, and first and second thermal interface devices 140, 160 collectively form a cooling system for the die 110. The power dissipation of microprocessors and other processing devices generally increases with each design generation, as the operating frequencies of these devices are ratcheted upwards. Also, the design and operating conditions for a die may lead to “hot spots” on the die where the local temperature is significantly greater than in surrounding regions on the die, and a failure to adequately extract heat from such hot spots may lead to damage and/or a degradation in performance of the die. Thus, the thermal performance of die cooling systems in future generations of IC devices will become increasingly critical, and the thermal performance required for these devices may push the limits of the conventional cooling system illustrated in FIG. 1.